Fysetc rename Part 2
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11 changed files with 13 additions and 13 deletions
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@ -237,7 +237,7 @@ else ifeq ($(HARDWARE_MOTHERBOARD),1134)
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else ifeq ($(HARDWARE_MOTHERBOARD),1135)
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# Dagoma F5
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else ifeq ($(HARDWARE_MOTHERBOARD),1136)
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# Fysetc F6
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# FYSETC F6
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else ifeq ($(HARDWARE_MOTHERBOARD),1137)
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# Duplicator i3 Plus
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else ifeq ($(HARDWARE_MOTHERBOARD),1138)
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@ -88,7 +88,7 @@
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#define BOARD_RAMPS_ENDER_4 1134 // Creality: Ender-4, CR-8
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#define BOARD_RAMPS_CREALITY 1135 // Creality: CR10S, CR20, CR-X
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#define BOARD_RAMPS_DAGOMA 1136 // Dagoma F5
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#define BOARD_FYSETC_F6_13 1137 // Fysetc F6
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#define BOARD_FYSETC_F6_13 1137 // FYSETC F6
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#define BOARD_DUPLICATOR_I3_PLUS 1138 // Wanhao Duplicator i3 Plus
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#define BOARD_VORON 1139 // VORON Design
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#define BOARD_TRONXY_V3_1_0 1140 // Tronxy TRONXY-V3-1.0
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@ -1561,7 +1561,7 @@ static_assert(Y_MAX_LENGTH >= Y_BED_SIZE, "Movement bounds (Y_MIN_POS, Y_MAX_POS
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* LED Backlight Timeout
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*/
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#if defined(LED_BACKLIGHT_TIMEOUT) && !(EITHER(FYSETC_MINI_12864_2_0, FYSETC_MINI_12864_2_1) && HAS_POWER_SWITCH)
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#error "LED_BACKLIGHT_TIMEOUT requires a Fysetc Mini Panel and a Power Switch."
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#error "LED_BACKLIGHT_TIMEOUT requires a FYSETC Mini Panel and a Power Switch."
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#endif
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/**
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@ -231,33 +231,33 @@
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#if ENABLED(FYSETC_MINI_12864)
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/**
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* The Fysetc display can NOT use the SCK and MOSI pins on EXP2, so a
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* The FYSETC display can NOT use the SCK and MOSI pins on EXP2, so a
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* special cable is needed to go between EXP2 on the FYSETC and the
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* controller board's EXP2 and J8. It also means that a software SPI
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* is needed to drive those pins.
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*
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* The Fysetc requires mode 3 SPI interface.
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* The FYSETC requires mode 3 SPI interface.
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*
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* Pins 6, 7 & 8 on EXP2 are no connects. That means a second special
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* cable will be needed if the RGB LEDs are to be active.
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*/
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#define DOGLCD_CS LCD_PINS_ENABLE // EXP1.3 (LCD_EN on Fysetc schematic)
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#define DOGLCD_A0 LCD_PINS_RS // EXP1.4 (LCD_A0 on Fysetc schematic)
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#define DOGLCD_SCK P2_11 // J8-5 (SCK on Fysetc schematic)
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#define DOGLCD_MOSI P4_28 // J8-6 (MOSI on Fysetc schematic)
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#define DOGLCD_CS LCD_PINS_ENABLE // EXP1.3 (LCD_EN on FYSETC schematic)
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#define DOGLCD_A0 LCD_PINS_RS // EXP1.4 (LCD_A0 on FYSETC schematic)
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#define DOGLCD_SCK P2_11 // J8-5 (SCK on FYSETC schematic)
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#define DOGLCD_MOSI P4_28 // J8-6 (MOSI on FYSETC schematic)
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//#define FORCE_SOFT_SPI // Use this if default of hardware SPI causes display problems
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// results in LCD soft SPI mode 3, SD soft SPI mode 0
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#if EITHER(FYSETC_MINI_12864_1_2, FYSETC_MINI_12864_2_0)
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#ifndef RGB_LED_R_PIN
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#define RGB_LED_R_PIN P2_12 // J8-4 (LCD_D6 on Fysetc schematic)
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#define RGB_LED_R_PIN P2_12 // J8-4 (LCD_D6 on FYSETC schematic)
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#endif
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#ifndef RGB_LED_G_PIN
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#define RGB_LED_G_PIN P1_23 // J8-3 (LCD_D5 on Fysetc schematic)
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#define RGB_LED_G_PIN P1_23 // J8-3 (LCD_D5 on FYSETC schematic)
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#endif
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#ifndef RGB_LED_B_PIN
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#define RGB_LED_B_PIN P1_22 // J8-2 (LCD_D7 on Fysetc schematic)
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#define RGB_LED_B_PIN P1_22 // J8-2 (LCD_D7 on FYSETC schematic)
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#endif
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#elif ENABLED(FYSETC_MINI_12864_2_1)
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#define NEOPIXEL_PIN P2_12
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@ -22,7 +22,7 @@
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#pragma once
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//
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// Fysetc F6 pin assignments
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// FYSETC F6 pin assignments
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//
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#ifndef __AVR_ATmega2560__
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