Backtrace formatting cleanup
This commit is contained in:
Scott Lahteine
parent
902c885782
commit
4b25543633
2 changed files with 79 additions and 80 deletions
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@ -46,7 +46,7 @@ void UnwInvalidateRegisterFile(RegData *regFile) {
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do {
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regFile[t].o = REG_VAL_INVALID;
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t++;
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} while(t < 13);
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} while (t < 13);
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}
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@ -107,7 +107,7 @@ bool UnwReportRetAddr(UnwState * const state, uint32_t addr) {
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// Scan backwards until we find the function name
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uint32_t v;
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while(state->cb->readW(pf-4,&v)) {
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while (state->cb->readW(pf-4,&v)) {
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// Check if name descriptor is valid
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if ((v & 0xFFFFFF00) == 0xFF000000 && (v & 0xFF) > 1) {
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@ -118,7 +118,7 @@ bool UnwReportRetAddr(UnwState * const state, uint32_t addr) {
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}
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// Go backwards to the previous word
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pf -= 4;;
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pf -= 4;
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}
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}
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@ -33,18 +33,18 @@
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*/
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static bool isDataProc(uint32_t instr) {
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uint8_t opcode = (instr & 0x01e00000) >> 21;
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uint8_t opcode = (instr & 0x01E00000) >> 21;
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bool S = (instr & 0x00100000) ? true : false;
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if((instr & 0xfc000000) != 0xe0000000) {
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if ((instr & 0xFC000000) != 0xE0000000) {
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return false;
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} else
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if(!S && opcode >= 8 && opcode <= 11) {
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}
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else if (!S && opcode >= 8 && opcode <= 11) {
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/* TST, TEQ, CMP and CMN all require S to be set */
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return false;
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} else {
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return true;
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}
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else
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return true;
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}
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UnwResult UnwStartArm(UnwState * const state) {
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@ -56,20 +56,20 @@ UnwResult UnwStartArm(UnwState * const state) {
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uint32_t instr;
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/* Attempt to read the instruction */
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if(!state->cb->readW(state->regData[15].v, &instr)) {
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if (!state->cb->readW(state->regData[15].v, &instr)) {
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return UNWIND_IREAD_W_FAIL;
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}
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UnwPrintd4("A %x %x %08x:", state->regData[13].v, state->regData[15].v, instr);
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/* Check that the PC is still on Arm alignment */
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if(state->regData[15].v & 0x3) {
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if (state->regData[15].v & 0x3) {
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UnwPrintd1("\nError: PC misalignment\n");
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return UNWIND_INCONSISTENT;
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}
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/* Check that the SP and PC have not been invalidated */
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if(!M_IsOriginValid(state->regData[13].o) || !M_IsOriginValid(state->regData[15].o)) {
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if (!M_IsOriginValid(state->regData[13].o) || !M_IsOriginValid(state->regData[15].o)) {
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UnwPrintd1("\nError: PC or SP invalidated\n");
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return UNWIND_INCONSISTENT;
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}
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@ -78,12 +78,12 @@ UnwResult UnwStartArm(UnwState * const state) {
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* This is tested prior to data processing to prevent
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* mis-interpretation as an invalid TEQ instruction.
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*/
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if((instr & 0xfffffff0) == 0xe12fff10) {
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uint8_t rn = instr & 0xf;
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if ((instr & 0xFFFFFFF0) == 0xE12FFF10) {
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uint8_t rn = instr & 0xF;
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UnwPrintd4("BX r%d\t ; r%d %s\n", rn, rn, M_Origin2Str(state->regData[rn].o));
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if(!M_IsOriginValid(state->regData[rn].o)) {
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if (!M_IsOriginValid(state->regData[rn].o)) {
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UnwPrintd1("\nUnwind failure: BX to untracked register\n");
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return UNWIND_FAILURE;
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}
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@ -92,19 +92,18 @@ UnwResult UnwStartArm(UnwState * const state) {
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state->regData[15].v = state->regData[rn].v;
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/* Check if the return value is from the stack */
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if(state->regData[rn].o == REG_VAL_FROM_STACK) {
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if (state->regData[rn].o == REG_VAL_FROM_STACK) {
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/* Now have the return address */
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UnwPrintd2(" Return PC=%x\n", state->regData[15].v & (~0x1));
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/* Report the return address */
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if(!UnwReportRetAddr(state, state->regData[rn].v)) {
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return UNWIND_TRUNCATED;
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}
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if (!UnwReportRetAddr(state, state->regData[rn].v))
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return UNWIND_TRUNCATED;
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}
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/* Determine the return mode */
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if(state->regData[rn].v & 0x1) {
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if (state->regData[rn].v & 0x1) {
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/* Branching to THUMB */
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return UnwStartThumb(state);
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@ -118,16 +117,16 @@ UnwResult UnwStartArm(UnwState * const state) {
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}
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}
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/* Branch */
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else if((instr & 0xff000000) == 0xea000000) {
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else if ((instr & 0xFF000000) == 0xEA000000) {
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int32_t offset = (instr & 0x00ffffff);
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int32_t offset = (instr & 0x00FFFFFF);
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/* Shift value */
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offset = offset << 2;
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/* Sign extend if needed */
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if(offset & 0x02000000) {
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offset |= 0xfc000000;
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if (offset & 0x02000000) {
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offset |= 0xFC000000;
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}
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UnwPrintd2("B %d\n", offset);
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@ -142,11 +141,11 @@ UnwResult UnwStartArm(UnwState * const state) {
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}
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/* MRS */
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else if((instr & 0xffbf0fff) == 0xe10f0000) {
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else if ((instr & 0xFFBF0FFF) == 0xE10F0000) {
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#if defined(UNW_DEBUG)
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bool R = (instr & 0x00400000) ? true : false;
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#endif
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uint8_t rd = (instr & 0x0000f000) >> 12;
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uint8_t rd = (instr & 0x0000F000) >> 12;
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UnwPrintd4("MRS r%d,%s\t; r%d invalidated", rd, R ? "SPSR" : "CPSR", rd);
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@ -154,7 +153,7 @@ UnwResult UnwStartArm(UnwState * const state) {
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state->regData[rd].o = REG_VAL_INVALID;
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}
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/* MSR */
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else if((instr & 0xffb0f000) == 0xe120f000) {
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else if ((instr & 0xFFB0F000) == 0xE120F000) {
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#if defined(UNW_DEBUG)
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bool R = (instr & 0x00400000) ? true : false;
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@ -170,15 +169,15 @@ UnwResult UnwStartArm(UnwState * const state) {
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*/
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}
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/* Data processing */
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else if(isDataProc(instr)) {
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else if (isDataProc(instr)) {
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bool I = (instr & 0x02000000) ? true : false;
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uint8_t opcode = (instr & 0x01e00000) >> 21;
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uint8_t opcode = (instr & 0x01E00000) >> 21;
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#if defined(UNW_DEBUG)
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bool S = (instr & 0x00100000) ? true : false;
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#endif
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uint8_t rn = (instr & 0x000f0000) >> 16;
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uint8_t rd = (instr & 0x0000f000) >> 12;
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uint16_t operand2 = (instr & 0x00000fff);
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uint8_t rn = (instr & 0x000F0000) >> 16;
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uint8_t rd = (instr & 0x0000F000) >> 12;
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uint16_t operand2 = (instr & 0x00000FFF);
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uint32_t op2val;
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int op2origin;
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@ -203,8 +202,8 @@ UnwResult UnwStartArm(UnwState * const state) {
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/* Decode operand 2 */
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if (I) {
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uint8_t shiftDist = (operand2 & 0x0f00) >> 8;
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uint8_t shiftConst = (operand2 & 0x00ff);
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uint8_t shiftDist = (operand2 & 0x0F00) >> 8;
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uint8_t shiftConst = (operand2 & 0x00FF);
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/* rotate const right by 2 * shiftDist */
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shiftDist *= 2;
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@ -217,7 +216,7 @@ UnwResult UnwStartArm(UnwState * const state) {
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else {
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/* Register and shift */
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uint8_t rm = (operand2 & 0x000f);
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uint8_t rm = (operand2 & 0x000F);
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uint8_t regShift = (operand2 & 0x0010) ? true : false;
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uint8_t shiftType = (operand2 & 0x0060) >> 5;
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uint32_t shiftDist;
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@ -227,16 +226,16 @@ UnwResult UnwStartArm(UnwState * const state) {
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UnwPrintd2("r%d ", rm);
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/* Get the shift distance */
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if(regShift) {
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if (regShift) {
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uint8_t rs = (operand2 & 0x0f00) >> 8;
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uint8_t rs = (operand2 & 0x0F00) >> 8;
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if(operand2 & 0x00800) {
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if (operand2 & 0x00800) {
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UnwPrintd1("\nError: Bit should be zero\n");
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return UNWIND_ILLEGAL_INSTR;
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}
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else if(rs == 15) {
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else if (rs == 15) {
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UnwPrintd1("\nError: Cannot use R15 with register shift\n");
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return UNWIND_ILLEGAL_INSTR;
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@ -249,10 +248,10 @@ UnwResult UnwStartArm(UnwState * const state) {
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UnwPrintd7("%s r%d\t; r%d %s r%d %s", shiftMnu[shiftType], rs, rm, M_Origin2Str(state->regData[rm].o), rs, M_Origin2Str(state->regData[rs].o));
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}
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else {
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shiftDist = (operand2 & 0x0f80) >> 7;
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shiftDist = (operand2 & 0x0F80) >> 7;
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op2origin = REG_VAL_FROM_CONST;
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if(shiftDist) {
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if (shiftDist) {
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UnwPrintd3("%s #%d", shiftMnu[shiftType], shiftDist);
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}
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UnwPrintd3("\t; r%d %s", rm, M_Origin2Str(state->regData[rm].o));
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@ -265,7 +264,7 @@ UnwResult UnwStartArm(UnwState * const state) {
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break;
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case 1: /* logical right */
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if(!regShift && shiftDist == 0) {
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if (!regShift && shiftDist == 0) {
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shiftDist = 32;
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}
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@ -273,19 +272,19 @@ UnwResult UnwStartArm(UnwState * const state) {
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break;
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case 2: /* arithmetic right */
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if(!regShift && shiftDist == 0) {
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if (!regShift && shiftDist == 0) {
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shiftDist = 32;
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}
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if(state->regData[rm].v & 0x80000000) {
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if (state->regData[rm].v & 0x80000000) {
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/* Register shifts maybe greater than 32 */
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if(shiftDist >= 32) {
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op2val = 0xffffffff;
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if (shiftDist >= 32) {
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op2val = 0xFFFFFFFF;
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}
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else {
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op2val = state->regData[rm].v >> shiftDist;
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op2val |= 0xffffffff << (32 - shiftDist);
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op2val |= 0xFFFFFFFF << (32 - shiftDist);
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}
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}
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else {
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@ -295,7 +294,7 @@ UnwResult UnwStartArm(UnwState * const state) {
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case 3: /* rotate right */
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if(!regShift && shiftDist == 0) {
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if (!regShift && shiftDist == 0) {
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/* Rotate right with extend.
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* This uses the carry bit and so always has an
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* untracked result.
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@ -305,7 +304,7 @@ UnwResult UnwStartArm(UnwState * const state) {
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}
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else {
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/* Limit shift distance to 0-31 incase of register shift */
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shiftDist &= 0x1f;
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shiftDist &= 0x1F;
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op2val = (state->regData[rm].v >> shiftDist) |
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(state->regData[rm].v << (32 - shiftDist));
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@ -318,7 +317,7 @@ UnwResult UnwStartArm(UnwState * const state) {
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}
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/* Decide the data origin */
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if(M_IsOriginValid(op2origin) &&
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if (M_IsOriginValid(op2origin) &&
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M_IsOriginValid(state->regData[rm].o)) {
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op2origin = state->regData[rm].o;
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@ -338,7 +337,7 @@ UnwResult UnwStartArm(UnwState * const state) {
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case 4: /* ADD: Rd:= Op1 + Op2 */
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case 12: /* ORR: Rd:= Op1 OR Op2 */
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case 14: /* BIC: Rd:= Op1 AND NOT Op2 */
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if(!M_IsOriginValid(state->regData[rn].o) ||
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if (!M_IsOriginValid(state->regData[rn].o) ||
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!M_IsOriginValid(op2origin)) {
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state->regData[rd].o = REG_VAL_INVALID;
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}
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@ -368,14 +367,14 @@ UnwResult UnwStartArm(UnwState * const state) {
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}
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/* Account for pre-fetch by temporarily adjusting PC */
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if(rn == 15) {
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if (rn == 15) {
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/* If the shift amount is specified in the instruction,
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* the PC will be 8 bytes ahead. If a register is used
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* to specify the shift amount the PC will be 12 bytes
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* ahead.
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*/
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if(!I && (operand2 & 0x0010))
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if (!I && (operand2 & 0x0010))
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state->regData[rn].v += 12;
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else
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state->regData[rn].v += 8;
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@ -430,8 +429,8 @@ UnwResult UnwStartArm(UnwState * const state) {
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}
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/* Remove the prefetch offset from the PC */
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if(rd != 15 && rn == 15) {
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if(!I && (operand2 & 0x0010))
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if (rd != 15 && rn == 15) {
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if (!I && (operand2 & 0x0010))
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state->regData[rn].v -= 12;
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else
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state->regData[rn].v -= 8;
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@ -441,22 +440,22 @@ UnwResult UnwStartArm(UnwState * const state) {
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/* Block Data Transfer
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* LDM, STM
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*/
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else if((instr & 0xfe000000) == 0xe8000000) {
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else if ((instr & 0xFE000000) == 0xE8000000) {
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bool P = (instr & 0x01000000) ? true : false;
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bool U = (instr & 0x00800000) ? true : false;
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bool S = (instr & 0x00400000) ? true : false;
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bool W = (instr & 0x00200000) ? true : false;
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bool L = (instr & 0x00100000) ? true : false;
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uint16_t baseReg = (instr & 0x000f0000) >> 16;
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uint16_t regList = (instr & 0x0000ffff);
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uint16_t baseReg = (instr & 0x000F0000) >> 16;
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uint16_t regList = (instr & 0x0000FFFF);
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uint32_t addr = state->regData[baseReg].v;
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bool addrValid = M_IsOriginValid(state->regData[baseReg].o);
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int8_t r;
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#if defined(UNW_DEBUG)
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/* Display the instruction */
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if(L) {
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if (L) {
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UnwPrintd6("LDM%c%c r%d%s, {reglist}%s\n", P ? 'E' : 'F', U ? 'D' : 'A', baseReg, W ? "!" : "", S ? "^" : "");
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}
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else {
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@ -467,15 +466,15 @@ UnwResult UnwStartArm(UnwState * const state) {
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* this is a load including the PC when the S-bit indicates that
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* that CPSR is loaded from SPSR (also untracked, but ignored).
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*/
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if(S && (!L || (regList & (0x01 << 15)) == 0)) {
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if (S && (!L || (regList & (0x01 << 15)) == 0)) {
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UnwPrintd1("\nError:S-bit set requiring banked registers\n");
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return UNWIND_FAILURE;
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}
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else if(baseReg == 15) {
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else if (baseReg == 15) {
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UnwPrintd1("\nError: r15 used as base register\n");
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return UNWIND_FAILURE;
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}
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else if(regList == 0) {
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else if (regList == 0) {
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UnwPrintd1("\nError: Register list empty\n");
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return UNWIND_FAILURE;
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}
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@ -488,21 +487,21 @@ UnwResult UnwStartArm(UnwState * const state) {
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do {
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/* Check if the register is to be transferred */
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if(regList & (0x01 << r)) {
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if (regList & (0x01 << r)) {
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if(P)
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if (P)
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addr += U ? 4 : -4;
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if(L) {
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if (L) {
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if(addrValid) {
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if (addrValid) {
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if(!UnwMemReadRegister(state, addr, &state->regData[r])) {
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if (!UnwMemReadRegister(state, addr, &state->regData[r])) {
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return UNWIND_DREAD_W_FAIL;
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}
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/* Update the origin if read via the stack pointer */
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if(M_IsOriginValid(state->regData[r].o) && baseReg == 13) {
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if (M_IsOriginValid(state->regData[r].o) && baseReg == 13) {
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state->regData[r].o = REG_VAL_FROM_STACK;
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}
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@ -517,8 +516,8 @@ UnwResult UnwStartArm(UnwState * const state) {
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}
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}
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else {
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if(addrValid) {
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if(!UnwMemWriteRegister(state, state->regData[13].v, &state->regData[r])) {
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if (addrValid) {
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if (!UnwMemWriteRegister(state, state->regData[13].v, &state->regData[r])) {
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return UNWIND_DWRITE_W_FAIL;
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}
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||||
}
|
||||
|
|
@ -526,36 +525,36 @@ UnwResult UnwStartArm(UnwState * const state) {
|
|||
UnwPrintd2(" R%d = 0x%08x\n", r);
|
||||
}
|
||||
|
||||
if(!P)
|
||||
if (!P)
|
||||
addr += U ? 4 : -4;
|
||||
}
|
||||
|
||||
/* Check the next register */
|
||||
r += U ? 1 : -1;
|
||||
|
||||
} while(r >= 0 && r <= 15);
|
||||
} while (r >= 0 && r <= 15);
|
||||
|
||||
/* Check the writeback bit */
|
||||
if(W)
|
||||
if (W)
|
||||
state->regData[baseReg].v = addr;
|
||||
|
||||
/* Check if the PC was loaded */
|
||||
if(L && (regList & (0x01 << 15))) {
|
||||
if(!M_IsOriginValid(state->regData[15].o)) {
|
||||
if (L && (regList & (0x01 << 15))) {
|
||||
if (!M_IsOriginValid(state->regData[15].o)) {
|
||||
/* Return address is not valid */
|
||||
UnwPrintd1("PC popped with invalid address\n");
|
||||
return UNWIND_FAILURE;
|
||||
}
|
||||
else {
|
||||
/* Store the return address */
|
||||
if(!UnwReportRetAddr(state, state->regData[15].v)) {
|
||||
if (!UnwReportRetAddr(state, state->regData[15].v)) {
|
||||
return UNWIND_TRUNCATED;
|
||||
}
|
||||
|
||||
UnwPrintd2(" Return PC=0x%x", state->regData[15].v);
|
||||
|
||||
/* Determine the return mode */
|
||||
if(state->regData[15].v & 0x1) {
|
||||
if (state->regData[15].v & 0x1) {
|
||||
/* Branching to THUMB */
|
||||
return UnwStartThumb(state);
|
||||
}
|
||||
|
|
@ -578,7 +577,7 @@ UnwResult UnwStartArm(UnwState * const state) {
|
|||
UnwPrintd1("\n");
|
||||
|
||||
/* Should never hit the reset vector */
|
||||
if(state->regData[15].v == 0) return UNWIND_RESET;
|
||||
if (state->regData[15].v == 0) return UNWIND_RESET;
|
||||
|
||||
/* Check next address */
|
||||
state->regData[15].v += 4;
|
||||
|
|
@ -587,10 +586,10 @@ UnwResult UnwStartArm(UnwState * const state) {
|
|||
UnwMemHashGC(state);
|
||||
|
||||
t--;
|
||||
if(t == 0)
|
||||
if (t == 0)
|
||||
return UNWIND_EXHAUSTED;
|
||||
|
||||
} while(!found);
|
||||
} while (!found);
|
||||
|
||||
return UNWIND_UNSUPPORTED;
|
||||
}
|
||||
|
|
|
|||
Reference in a new issue