diff --git a/Marlin/src/HAL/HAL_DUE/usb/uotghs_device_due.h b/Marlin/src/HAL/HAL_DUE/usb/uotghs_device_due.h index 9ed7f1124..1cd6914f8 100644 --- a/Marlin/src/HAL/HAL_DUE/usb/uotghs_device_due.h +++ b/Marlin/src/HAL/HAL_DUE/usb/uotghs_device_due.h @@ -217,7 +217,7 @@ extern "C" { #define udd_raise_msof() (UOTGHS->UOTGHS_DEVIFR = UOTGHS_DEVIFR_MSOFS) #define Is_udd_msof() (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_MSOF)) #define udd_micro_frame_number() \ - (Rd_bitfield(UOTGHS->UOTGHS_DEVFNUM, (UOTGHS_DEVFNUM_FNUM_Msk|UOTGHS_DEVFNUM_MFNUM_Msk))) + (Rd_bitfield(UOTGHS->UOTGHS_DEVFNUM, (UOTGHS_DEVFNUM_FNUM_Msk|UOTGHS_DEVFNUM_MFNUM_Msk))) //! @} //! Manage suspend event @@ -266,10 +266,10 @@ extern "C" { #define Is_udd_endpoint_enabled(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPT, UOTGHS_DEVEPT_EPEN0 << (ep))) //! resets the selected endpoint #define udd_reset_endpoint(ep) \ - do { \ - Set_bits(UOTGHS->UOTGHS_DEVEPT, UOTGHS_DEVEPT_EPRST0 << (ep)); \ - Clr_bits(UOTGHS->UOTGHS_DEVEPT, UOTGHS_DEVEPT_EPRST0 << (ep)); \ - } while (0) + do { \ + Set_bits(UOTGHS->UOTGHS_DEVEPT, UOTGHS_DEVEPT_EPRST0 << (ep)); \ + Clr_bits(UOTGHS->UOTGHS_DEVEPT, UOTGHS_DEVEPT_EPRST0 << (ep)); \ + } while (0) //! Tests if the selected endpoint is being reset #define Is_udd_resetting_endpoint(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPT, UOTGHS_DEVEPT_EPRST0 << (ep))) @@ -290,6 +290,7 @@ extern "C" { //! Bounds given integer size to allowed range and rounds it up to the nearest //! available greater size, then applies register format of UOTGHS controller //! for endpoint size bit-field. +#undef udd_format_endpoint_size #define udd_format_endpoint_size(size) (32 - clz(((uint32_t)MIN(MAX(size, 8), 1024) << 1) - 1) - 1 - 3) //! Configures the selected endpoint size #define udd_configure_endpoint_size(ep, size) (Wr_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPSIZE_Msk, udd_format_endpoint_size(size))) @@ -307,14 +308,14 @@ extern "C" { //! Configures selected endpoint in one step #define udd_configure_endpoint(ep, type, dir, size, bank) (\ - Wr_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPTYPE_Msk |\ - UOTGHS_DEVEPTCFG_EPDIR |\ - UOTGHS_DEVEPTCFG_EPSIZE_Msk |\ - UOTGHS_DEVEPTCFG_EPBK_Msk , \ - (((uint32_t)(type) << UOTGHS_DEVEPTCFG_EPTYPE_Pos) & UOTGHS_DEVEPTCFG_EPTYPE_Msk) |\ - (((uint32_t)(dir ) << UOTGHS_DEVEPTCFG_EPDIR_Pos ) & UOTGHS_DEVEPTCFG_EPDIR) |\ - ( (uint32_t)udd_format_endpoint_size(size) << UOTGHS_DEVEPTCFG_EPSIZE_Pos) |\ - (((uint32_t)(bank) << UOTGHS_DEVEPTCFG_EPBK_Pos) & UOTGHS_DEVEPTCFG_EPBK_Msk))\ + Wr_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPTYPE_Msk |\ + UOTGHS_DEVEPTCFG_EPDIR |\ + UOTGHS_DEVEPTCFG_EPSIZE_Msk |\ + UOTGHS_DEVEPTCFG_EPBK_Msk , \ + (((uint32_t)(type) << UOTGHS_DEVEPTCFG_EPTYPE_Pos) & UOTGHS_DEVEPTCFG_EPTYPE_Msk) |\ + (((uint32_t)(dir ) << UOTGHS_DEVEPTCFG_EPDIR_Pos ) & UOTGHS_DEVEPTCFG_EPDIR) |\ + ( (uint32_t)udd_format_endpoint_size(size) << UOTGHS_DEVEPTCFG_EPSIZE_Pos) |\ + (((uint32_t)(bank) << UOTGHS_DEVEPTCFG_EPBK_Pos) & UOTGHS_DEVEPTCFG_EPBK_Msk))\ ) //! Tests if current endpoint is configured #define Is_udd_endpoint_configured(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_CFGOK)) @@ -540,7 +541,7 @@ extern "C" { //! @warning It is up to the user of this macro to make sure that used HSB //! addresses are identical to the DPRAM internal pointer modulo 32 bits. #define udd_get_endpoint_fifo_access(ep, scale) \ - (((volatile TPASTE2(U, scale) (*)[0x8000 / ((scale) / 8)])UOTGHS_RAM_ADDR)[(ep)]) + (((volatile TPASTE2(U, scale) (*)[0x8000 / ((scale) / 8)])UOTGHS_RAM_ADDR)[(ep)]) //! @name UOTGHS endpoint DMA drivers //! These macros manage the common features of the endpoint DMA channels. @@ -572,60 +573,60 @@ extern "C" { //! @{ //! Structure for DMA next descriptor register typedef struct { - uint32_t *NXT_DSC_ADD; + uint32_t *NXT_DSC_ADD; } uotghs_dma_nextdesc_t; //! Structure for DMA control register typedef struct { - uint32_t CHANN_ENB:1, - LDNXT_DSC:1, - END_TR_EN:1, - END_B_EN:1, - END_TR_IT:1, - END_BUFFIT:1, - DESC_LD_IT:1, - BUST_LCK:1, - reserved:8, - BUFF_LENGTH:16; + uint32_t CHANN_ENB:1, + LDNXT_DSC:1, + END_TR_EN:1, + END_B_EN:1, + END_TR_IT:1, + END_BUFFIT:1, + DESC_LD_IT:1, + BUST_LCK:1, + reserved:8, + BUFF_LENGTH:16; } uotghs_dma_control_t; //! Structure for DMA status register typedef struct { - uint32_t CHANN_ENB:1, - CHANN_ACT:1, - reserved0:2, - END_TR_ST:1, - END_BF_ST:1, - DESC_LDST:1, - reserved1:9, - BUFF_COUNT:16; + uint32_t CHANN_ENB:1, + CHANN_ACT:1, + reserved0:2, + END_TR_ST:1, + END_BF_ST:1, + DESC_LDST:1, + reserved1:9, + BUFF_COUNT:16; } uotghs_dma_status_t; //! Structure for DMA descriptor typedef struct { - union { - uint32_t nextdesc; - uotghs_dma_nextdesc_t NEXTDESC; - }; - uint32_t addr; - union { - uint32_t control; - uotghs_dma_control_t CONTROL; - }; - uint32_t reserved; + union { + uint32_t nextdesc; + uotghs_dma_nextdesc_t NEXTDESC; + }; + uint32_t addr; + union { + uint32_t control; + uotghs_dma_control_t CONTROL; + }; + uint32_t reserved; } sam_uotghs_dmadesc_t, uotghs_dmadesc_t; //! Structure for DMA registers in a channel typedef struct { - union { - uint32_t nextdesc; - uotghs_dma_nextdesc_t NEXTDESC; - }; - uint32_t addr; - union { - uint32_t control; - uotghs_dma_control_t CONTROL; - }; - union { - unsigned long status; - uotghs_dma_status_t STATUS; - }; + union { + uint32_t nextdesc; + uotghs_dma_nextdesc_t NEXTDESC; + }; + uint32_t addr; + union { + uint32_t control; + uotghs_dma_control_t CONTROL; + }; + union { + unsigned long status; + uotghs_dma_status_t STATUS; + }; } sam_uotghs_dmach_t, uotghs_dmach_t; //! DMA channel control command #define UDD_ENDPOINT_DMA_STOP_NOW (0) diff --git a/Marlin/src/HAL/HAL_LPC1768/u8g_com_HAL_LPC1768_st7920_sw_spi.cpp b/Marlin/src/HAL/HAL_LPC1768/u8g_com_HAL_LPC1768_st7920_sw_spi.cpp index aaa37e256..700ed5946 100644 --- a/Marlin/src/HAL/HAL_LPC1768/u8g_com_HAL_LPC1768_st7920_sw_spi.cpp +++ b/Marlin/src/HAL/HAL_LPC1768/u8g_com_HAL_LPC1768_st7920_sw_spi.cpp @@ -70,7 +70,6 @@ static uint8_t SPI_speed = 0; static uint8_t rs_last_state = 255; static void u8g_com_LPC1768_st7920_write_byte_sw_spi(uint8_t rs, uint8_t val) { - uint8_t i; if (rs != rs_last_state) { // time to send a command/data byte rs_last_state = rs; diff --git a/Marlin/src/feature/bedlevel/ubl/ubl_motion.cpp b/Marlin/src/feature/bedlevel/ubl/ubl_motion.cpp index 85a6fad8e..a94144f58 100644 --- a/Marlin/src/feature/bedlevel/ubl/ubl_motion.cpp +++ b/Marlin/src/feature/bedlevel/ubl/ubl_motion.cpp @@ -443,7 +443,7 @@ uint16_t segments = lroundf(cartesian_xy_mm * (1.0 / (DELTA_SEGMENT_MIN_LENGTH))); // cartesian fixed segment length #endif - NOLESS(segments, 1); // must have at least one segment + NOLESS(segments, 1U); // must have at least one segment const float inv_segments = 1.0 / segments; // divide once, multiply thereafter #if IS_SCARA // scale the feed rate from mm/s to degrees/s diff --git a/Marlin/src/gcode/lcd/M300.cpp b/Marlin/src/gcode/lcd/M300.cpp index 847efc9c4..0e5658793 100644 --- a/Marlin/src/gcode/lcd/M300.cpp +++ b/Marlin/src/gcode/lcd/M300.cpp @@ -37,7 +37,7 @@ void GcodeSuite::M300() { uint16_t duration = parser.ushortval('P', 1000); // Limits the tone duration to 0-5 seconds. - NOMORE(duration, 5000); + NOMORE(duration, 5000U); BUZZ(duration, frequency); } diff --git a/Marlin/src/module/motion.cpp b/Marlin/src/module/motion.cpp index b91b84d7c..b6f53b4ac 100644 --- a/Marlin/src/module/motion.cpp +++ b/Marlin/src/module/motion.cpp @@ -570,7 +570,7 @@ float soft_endstop_min[XYZ] = { X_MIN_BED, Y_MIN_BED, Z_MIN_POS }, #endif // At least one segment is required - NOLESS(segments, 1); + NOLESS(segments, 1U); // The approximate length of each segment const float inv_segments = 1.0 / float(segments), @@ -717,7 +717,7 @@ float soft_endstop_min[XYZ] = { X_MIN_BED, Y_MIN_BED, Z_MIN_POS }, // The length divided by the segment size // At least one segment is required uint16_t segments = cartesian_mm / segment_size; - NOLESS(segments, 1); + NOLESS(segments, 1U); // The approximate length of each segment const float inv_segments = 1.0 / float(segments),