Convert custom maths to inlines (#10728)
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4 changed files with 100 additions and 100 deletions
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@ -23,92 +23,95 @@
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#ifndef _MATH_AVR_H_
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#define _MATH_AVR_H_
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#define a(CODE) " " CODE "\n\t"
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/**
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* Optimized math functions for AVR
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*/
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// intRes = longIn1 * longIn2 >> 24
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// uses:
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// r26 to store 0
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// r27 to store bits 16-23 of the 48bit result. The top bit is used to round the two byte result.
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// A[tmp] to store 0
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// B[tmp] to store bits 16-23 of the 48bit result. The top bit is used to round the two byte result.
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// note that the lower two bytes and the upper byte of the 48bit result are not calculated.
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// this can cause the result to be out by one as the lower bytes may cause carries into the upper ones.
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// B0 A0 are bits 24-39 and are the returned value
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// C1 B1 A1 is longIn1
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// D2 C2 B2 A2 is longIn2
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// B A are bits 24-39 and are the returned value
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// C B A is longIn1
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// D C B A is longIn2
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//
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#define MultiU24X32toH16(intRes, longIn1, longIn2) \
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asm volatile ( \
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A("clr r26") \
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A("mul %A1, %B2") \
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A("mov r27, r1") \
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A("mul %B1, %C2") \
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A("movw %A0, r0") \
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A("mul %C1, %C2") \
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A("add %B0, r0") \
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A("mul %C1, %B2") \
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A("add %A0, r0") \
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A("adc %B0, r1") \
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A("mul %A1, %C2") \
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A("add r27, r0") \
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A("adc %A0, r1") \
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A("adc %B0, r26") \
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A("mul %B1, %B2") \
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A("add r27, r0") \
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A("adc %A0, r1") \
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A("adc %B0, r26") \
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A("mul %C1, %A2") \
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A("add r27, r0") \
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A("adc %A0, r1") \
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A("adc %B0, r26") \
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A("mul %B1, %A2") \
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A("add r27, r1") \
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A("adc %A0, r26") \
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A("adc %B0, r26") \
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A("lsr r27") \
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A("adc %A0, r26") \
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A("adc %B0, r26") \
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A("mul %D2, %A1") \
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A("add %A0, r0") \
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A("adc %B0, r1") \
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A("mul %D2, %B1") \
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A("add %B0, r0") \
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A("clr r1") \
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: \
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"=&r" (intRes) \
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: \
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"d" (longIn1), \
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"d" (longIn2) \
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: \
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"r26" , "r27" \
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)
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static FORCE_INLINE uint16_t MultiU24X32toH16(uint32_t longIn1, uint32_t longIn2) {
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register uint8_t tmp1;
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register uint8_t tmp2;
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register uint16_t intRes;
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__asm__ __volatile__(
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A("clr %[tmp1]")
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A("mul %A[longIn1], %B[longIn2]")
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A("mov %[tmp2], r1")
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A("mul %B[longIn1], %C[longIn2]")
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A("movw %A[intRes], r0")
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A("mul %C[longIn1], %C[longIn2]")
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A("add %B[intRes], r0")
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A("mul %C[longIn1], %B[longIn2]")
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A("add %A[intRes], r0")
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A("adc %B[intRes], r1")
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A("mul %A[longIn1], %C[longIn2]")
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A("add %[tmp2], r0")
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A("adc %A[intRes], r1")
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A("adc %B[intRes], %[tmp1]")
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A("mul %B[longIn1], %B[longIn2]")
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A("add %[tmp2], r0")
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A("adc %A[intRes], r1")
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A("adc %B[intRes], %[tmp1]")
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A("mul %C[longIn1], %A[longIn2]")
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A("add %[tmp2], r0")
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A("adc %A[intRes], r1")
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A("adc %B[intRes], %[tmp1]")
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A("mul %B[longIn1], %A[longIn2]")
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A("add %[tmp2], r1")
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A("adc %A[intRes], %[tmp1]")
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A("adc %B[intRes], %[tmp1]")
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A("lsr %[tmp2]")
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A("adc %A[intRes], %[tmp1]")
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A("adc %B[intRes], %[tmp1]")
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A("mul %D[longIn2], %A[longIn1]")
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A("add %A[intRes], r0")
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A("adc %B[intRes], r1")
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A("mul %D[longIn2], %B[longIn1]")
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A("add %B[intRes], r0")
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A("clr r1")
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: [intRes] "=&r" (intRes),
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[tmp1] "=&r" (tmp1),
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[tmp2] "=&r" (tmp2)
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: [longIn1] "d" (longIn1),
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[longIn2] "d" (longIn2)
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: "cc"
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);
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return intRes;
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}
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// intRes = intIn1 * intIn2 >> 16
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// uses:
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// r26 to store 0
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// r27 to store the byte 1 of the 24 bit result
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#define MultiU16X8toH16(intRes, charIn1, intIn2) \
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asm volatile ( \
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A("clr r26") \
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A("mul %A1, %B2") \
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A("movw %A0, r0") \
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A("mul %A1, %A2") \
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A("add %A0, r1") \
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A("adc %B0, r26") \
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A("lsr r0") \
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A("adc %A0, r26") \
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A("adc %B0, r26") \
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A("clr r1") \
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: \
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"=&r" (intRes) \
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: \
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"d" (charIn1), \
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"d" (intIn2) \
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: \
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"r26" \
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)
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static FORCE_INLINE uint16_t MultiU16X8toH16(uint8_t charIn1, uint16_t intIn2) {
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register uint8_t tmp;
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register uint16_t intRes;
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__asm__ __volatile__ (
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A("clr %[tmp]")
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A("mul %[charIn1], %B[intIn2]")
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A("movw %A[intRes], r0")
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A("mul %[charIn1], %A[intIn2]")
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A("add %A[intRes], r1")
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A("adc %B[intRes], %[tmp]")
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A("lsr r0")
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A("adc %A[intRes], %[tmp]")
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A("adc %B[intRes], %[tmp]")
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A("clr r1")
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: [intRes] "=&r" (intRes),
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[tmp] "=&r" (tmp)
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: [charIn1] "d" (charIn1),
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[intIn2] "d" (intIn2)
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: "cc"
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);
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return intRes;
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}
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#endif // _MATH_AVR_H_
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@ -23,11 +23,13 @@
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#ifndef MATH_32BIT_H
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#define MATH_32BIT_H
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#include "../core/macros.h"
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/**
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* Math helper functions for 32 bit CPUs
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*/
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#define MultiU32X32toH32(intRes, longIn1, longIn2) intRes = ((uint64_t)longIn1 * longIn2 + 0x80000000) >> 32
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#define MultiU32X24toH32(intRes, longIn1, longIn2) intRes = ((uint64_t)longIn1 * longIn2 + 0x00800000) >> 24
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static FORCE_INLINE uint32_t MultiU32X24toH32(uint32_t longIn1, uint32_t longIn2) {
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return ((uint64_t)longIn1 * longIn2 + 0x00800000) >> 24;
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}
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#endif // MATH_32BIT_H
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@ -1158,6 +1158,12 @@ HAL_STEP_TIMER_ISR {
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HAL_timer_isr_epilogue(STEP_TIMER_NUM);
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}
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#ifdef CPU_32_BIT
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#define STEP_MULTIPLY(A,B) MultiU32X24toH32(A, B);
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#else
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#define STEP_MULTIPLY(A,B) MultiU24X32toH16(A, B);
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#endif
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void Stepper::isr() {
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#define ENDSTOP_NOMINAL_OCR_VAL 1500 * HAL_TICKS_PER_US // Check endstops every 1.5ms to guarantee two stepper ISRs within 5ms for BLTouch
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@ -1525,14 +1531,7 @@ void Stepper::isr() {
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? _eval_bezier_curve(acceleration_time)
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: current_block->cruise_rate;
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#else
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#ifdef CPU_32_BIT
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MultiU32X24toH32(acc_step_rate, acceleration_time, current_block->acceleration_rate);
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#else
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MultiU24X32toH16(acc_step_rate, acceleration_time, current_block->acceleration_rate);
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#endif
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acc_step_rate += current_block->initial_rate;
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// upper limit
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acc_step_rate = STEP_MULTIPLY(acceleration_time, current_block->acceleration_rate) + current_block->initial_rate;
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NOMORE(acc_step_rate, current_block->nominal_rate);
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#endif
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#else
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// Using the old trapezoidal control
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#ifdef CPU_32_BIT
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MultiU32X24toH32(step_rate, deceleration_time, current_block->acceleration_rate);
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#else
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MultiU24X32toH16(step_rate, deceleration_time, current_block->acceleration_rate);
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#endif
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step_rate = STEP_MULTIPLY(deceleration_time, current_block->acceleration_rate);
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if (step_rate < acc_step_rate) { // Still decelerating?
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step_rate = acc_step_rate - step_rate;
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NOLESS(step_rate, current_block->final_rate);
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}
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else
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step_rate = current_block->final_rate;
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#endif
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// step_rate to timer interval
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@ -340,24 +340,24 @@ class Stepper {
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#ifdef CPU_32_BIT
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// In case of high-performance processor, it is able to calculate in real-time
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const uint32_t MIN_TIME_PER_STEP = (HAL_STEPPER_TIMER_RATE) / ((STEP_DOUBLER_FREQUENCY) * 2);
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const uint32_t min_time_per_step = (HAL_STEPPER_TIMER_RATE) / ((STEP_DOUBLER_FREQUENCY) * 2);
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timer = uint32_t(HAL_STEPPER_TIMER_RATE) / step_rate;
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NOLESS(timer, MIN_TIME_PER_STEP); // (STEP_DOUBLER_FREQUENCY * 2 kHz - this should never happen)
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NOLESS(timer, min_time_per_step); // (STEP_DOUBLER_FREQUENCY * 2 kHz - this should never happen)
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#else
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NOLESS(step_rate, F_CPU / 500000);
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step_rate -= F_CPU / 500000; // Correct for minimal speed
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if (step_rate >= (8 * 256)) { // higher step rate
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unsigned short table_address = (unsigned short)&speed_lookuptable_fast[(unsigned char)(step_rate >> 8)][0];
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unsigned char tmp_step_rate = (step_rate & 0x00FF);
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unsigned short gain = (unsigned short)pgm_read_word_near(table_address + 2);
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MultiU16X8toH16(timer, tmp_step_rate, gain);
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timer = (unsigned short)pgm_read_word_near(table_address) - timer;
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uint8_t tmp_step_rate = (step_rate & 0x00FF);
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uint16_t table_address = (uint16_t)&speed_lookuptable_fast[(uint8_t)(step_rate >> 8)][0];
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uint16_t gain = (uint16_t)pgm_read_word_near(table_address + 2);
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timer = MultiU16X8toH16(tmp_step_rate, gain);
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timer = (uint16_t)pgm_read_word_near(table_address) - timer;
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}
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else { // lower step rates
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unsigned short table_address = (unsigned short)&speed_lookuptable_slow[0][0];
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uint16_t table_address = (uint16_t)&speed_lookuptable_slow[0][0];
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table_address += ((step_rate) >> 1) & 0xFFFC;
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timer = (unsigned short)pgm_read_word_near(table_address);
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timer -= (((unsigned short)pgm_read_word_near(table_address + 2) * (unsigned char)(step_rate & 0x0007)) >> 3);
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timer = (uint16_t)pgm_read_word_near(table_address);
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timer -= (((uint16_t)pgm_read_word_near(table_address + 2) * (uint8_t)(step_rate & 0x0007)) >> 3);
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}
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if (timer < 100) { // (20kHz - this should never happen)
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timer = 100;
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