Initial HAL SPI API
This commit is contained in:
Christopher Pepper
Scott Lahteine
parent
44b0c186a6
commit
bcd050f33b
5 changed files with 465 additions and 20 deletions
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@ -37,12 +37,12 @@
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// --------------------------------------------------------------------------
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#include "../../../MarlinConfig.h"
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#include "../spi_api.h"
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// --------------------------------------------------------------------------
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// Public Variables
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// --------------------------------------------------------------------------
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// --------------------------------------------------------------------------
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// Public functions
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// --------------------------------------------------------------------------
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@ -138,39 +138,32 @@
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}
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#else
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void spiBegin() {
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HAL::SPI::initialise(SD_SPI_CHANNEL);
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}
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void spiInit(uint8_t spiRate) {
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uint32_t freq = 8000000 / (1u << spiRate);
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HAL::SPI::set_frequency(SD_SPI_CHANNEL, freq);
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}
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void spiSend(byte b) {
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}
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void spiSend(const uint8_t* buf, size_t n) {
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}
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void spiSend(uint32_t chan, byte b) {
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}
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void spiSend(uint32_t chan, const uint8_t* buf, size_t n) {
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HAL::SPI::write(SD_SPI_CHANNEL, b);
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}
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// Read single byte from SPI
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uint8_t spiRec() {
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return 0;
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}
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uint8_t spiRec(uint32_t chan) {
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return 0;
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return HAL::SPI::read(SD_SPI_CHANNEL);
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}
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// Read from SPI into buffer
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void spiRead(uint8_t*buf, uint16_t nbyte) {
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HAL::SPI::read(SD_SPI_CHANNEL, buf, nbyte);
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}
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// Write from buffer to SPI
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void spiSendBlock(uint8_t token, const uint8_t* buf) {
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HAL::SPI::write(SD_SPI_CHANNEL, token);
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HAL::SPI::write(SD_SPI_CHANNEL, buf, 512);
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}
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#endif // ENABLED(SOFTWARE_SPI)
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@ -43,7 +43,6 @@ static __INLINE uint32_t SysTick_Config(uint32_t ticks) {
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SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
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return (0); /* Function successful */
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}
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extern "C" {
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extern void disk_timerproc(void);
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volatile uint32_t _millis;
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@ -70,6 +69,7 @@ extern "C" void SystemPostInit() {
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extern uint32_t MSC_SD_Init(uint8_t pdrv);
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extern HalSerial usb_serial;
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int main(void) {
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debug_frmwrk_init();
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(void)MSC_SD_Init(0);
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USB_Init(); // USB Initialization
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@ -81,8 +81,7 @@ int main(void) {
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TOGGLE(13); // Flash fast while USB initialisation completes
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}
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debug_frmwrk_init();
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usb_serial.printf("\n\nRe-ARM (LPC1768 @ %dMhz) UART0 Initialised\n", SystemCoreClock / 1000000);
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usb_serial.printf("\n\nRe-ARM (LPC1768 @ %dMhz) USB Initialised\n", SystemCoreClock / 1000000);
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HAL_timer_init();
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402
Marlin/src/HAL/HAL_LPC1768/spi_impl.cpp
Normal file
402
Marlin/src/HAL/HAL_LPC1768/spi_impl.cpp
Normal file
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@ -0,0 +1,402 @@
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#ifdef TARGET_LPC1768
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#include "../spi_api.h"
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#include <lpc17xx_ssp.h>
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#include <lpc17xx_pinsel.h>
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#include <lpc17xx_gpio.h>
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#include "lpc17xx_clkpwr.h"
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extern "C" void SSP0_IRQHandler(void);
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extern "C" void SSP1_IRQHandler(void);
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namespace HAL {
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namespace SPI {
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enum class SignalPolarity : uint8_t {
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ACTIVE_LOW = 0,
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ACTIVE_HIGH
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};
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/* Hardware channels :
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* 0: clk(0_7), mosi(0_9), miso(0_8), SSP1
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* 1: clk(0_15), mosi(0_28), miso(0_17), SSP0
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* Logical channels:
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* 0: hwchannel: 1, ssel(0_6)
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* 1: hwchannel: 0, ssel(0_16)
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* 2: hwchannel: 0, ssel(1_23)
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*/
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/*
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* Defines the Hardware setup for an SPI channel
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* The pins and (if applicable) the Hardware Peripheral
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*
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*/
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struct LogicalChannel; // who doesn't like circular dependencies
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struct HardwareChannel {
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LPC_SSP_TypeDef *peripheral;
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IRQn_Type IRQn;
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uint8_t clk_port;
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uint8_t clk_pin;
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uint8_t mosi_port;
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uint8_t mosi_pin;
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uint8_t miso_port;
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uint8_t miso_pin;
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SSP_DATA_SETUP_Type xfer_config;
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volatile FlagStatus xfer_complete;
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bool initialised;
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volatile bool in_use;
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LogicalChannel* active_channel;
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} hardware_channels[2] = {
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{LPC_SSP0, SSP0_IRQn, 0, 15, 0, 18, 0, 17, { nullptr, 0, nullptr, 0, 0, SSP_STAT_DONE }, RESET, false, false, nullptr},
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{LPC_SSP1, SSP1_IRQn, 0, 7, 0, 9, 0, 8 , { nullptr, 0, nullptr, 0, 0, SSP_STAT_DONE }, RESET, false, false, nullptr}
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};
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/*
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* Define all available logical SPI ports
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*/
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struct LogicalChannel {
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HardwareChannel& hw_channel;
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uint8_t ssel_port;
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uint8_t ssel_pin;
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SignalPolarity ssel_polarity;
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bool ssel_override;
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SSP_CFG_Type config;
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uint32_t CR0;
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uint32_t CPSR;
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} logical_channels[3] = {
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{ hardware_channels[1], 0, 6, SignalPolarity::ACTIVE_LOW, false, { SSP_DATABIT_8, SSP_CPHA_FIRST, SSP_CPOL_HI, SSP_MASTER_MODE, SSP_FRAME_SPI, 1000000 }, 0, 0 },
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{ hardware_channels[0], 0, 16, SignalPolarity::ACTIVE_HIGH, true, { SSP_DATABIT_8, SSP_CPHA_FIRST, SSP_CPOL_HI, SSP_MASTER_MODE, SSP_FRAME_SPI, 1000000 }, 0, 0 },
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{ hardware_channels[0], 1, 23, SignalPolarity::ACTIVE_LOW, true, { SSP_DATABIT_8, SSP_CPHA_FIRST, SSP_CPOL_HI, SSP_MASTER_MODE, SSP_FRAME_SPI, 1000000 }, 0, 0 }
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};
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//Internal functions
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extern "C" void ssp_irq_handler(uint8_t hw_channel);
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LogicalChannel* get_logical_channel(uint8_t channel);
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bool set_ssel(LogicalChannel* logical_channel);
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void clear_ssel(LogicalChannel* logical_channel);
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void restore_frequency(LogicalChannel* logical_channel);
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LogicalChannel* get_logical_channel(uint8_t channel) {
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if(channel > sizeof(logical_channels) - 1) {
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return nullptr;
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}
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return &logical_channels[channel];
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}
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bool set_ssel(LogicalChannel* logical_channel) {
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if(logical_channel->hw_channel.in_use == true) {
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return false;
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}
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if(logical_channel->ssel_polarity == SignalPolarity::ACTIVE_HIGH) {
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GPIO_SetValue(logical_channel->ssel_port, (1 << logical_channel->ssel_pin));
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} else {
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GPIO_ClearValue(logical_channel->ssel_port, (1 << logical_channel->ssel_pin));
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}
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logical_channel->hw_channel.in_use = true;
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return true;
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}
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void clear_ssel(LogicalChannel* logical_channel) {
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if(logical_channel->ssel_polarity == SignalPolarity::ACTIVE_HIGH) {
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GPIO_ClearValue(logical_channel->ssel_port, (1 << logical_channel->ssel_pin));
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} else {
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GPIO_SetValue(logical_channel->ssel_port, (1 << logical_channel->ssel_pin));
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}
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logical_channel->hw_channel.in_use = false;
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}
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void restore_frequency(LogicalChannel* logical_channel) {
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logical_channel->hw_channel.peripheral->CR0 = logical_channel->CR0;
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logical_channel->hw_channel.peripheral->CPSR = logical_channel->CPSR;
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}
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/*
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* SPI API Implementation
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*/
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bool initialise(uint8_t channel) {
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LogicalChannel* logical_channel = get_logical_channel(channel);
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if(logical_channel == nullptr) return false;
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HardwareChannel& hw_channel = logical_channel->hw_channel;
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PINSEL_CFG_Type pin_cfg;
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pin_cfg.OpenDrain = PINSEL_PINMODE_NORMAL;
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pin_cfg.Pinmode = PINSEL_PINMODE_PULLUP;
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if(hw_channel.initialised == false) {
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pin_cfg.Funcnum = 2; //ssp (spi) function
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pin_cfg.Portnum = hw_channel.clk_port;
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pin_cfg.Pinnum = hw_channel.clk_pin;
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PINSEL_ConfigPin(&pin_cfg); //clk
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pin_cfg.Portnum = hw_channel.miso_port;
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pin_cfg.Pinnum = hw_channel.miso_pin;
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PINSEL_ConfigPin(&pin_cfg); //miso
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pin_cfg.Portnum = hw_channel.mosi_port;
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pin_cfg.Pinnum = hw_channel.mosi_pin;
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PINSEL_ConfigPin(&pin_cfg); //mosi
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SSP_Init(hw_channel.peripheral, &logical_channel->config);
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logical_channel->CR0 = logical_channel->hw_channel.peripheral->CR0; // preserve for restore
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logical_channel->CPSR = logical_channel->hw_channel.peripheral->CPSR; // preserve for restore
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SSP_Cmd(hw_channel.peripheral, ENABLE);
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hw_channel.initialised = true;
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hw_channel.active_channel = logical_channel;
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//NVIC_SetPriority(hw_channel.IRQn, NVIC_EncodePriority(0, 3, 0)); //Very Low priority
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//NVIC_EnableIRQ(hw_channel.IRQn);
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}
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pin_cfg.Portnum = logical_channel->ssel_port;
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pin_cfg.Pinnum = logical_channel->ssel_pin;
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pin_cfg.Pinmode = logical_channel->ssel_polarity == SignalPolarity::ACTIVE_LOW ? PINSEL_PINMODE_PULLUP : PINSEL_PINMODE_PULLDOWN;
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pin_cfg.Funcnum = 0; //gpio function
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PINSEL_ConfigPin(&pin_cfg); //ssel
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GPIO_SetDir(logical_channel->ssel_port, (1 << logical_channel->ssel_pin), 1);
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GPIO_SetValue(logical_channel->ssel_port, (1 << logical_channel->ssel_pin));
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return true;
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}
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bool enable_cs(uint8_t channel) {
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LogicalChannel* logical_channel = get_logical_channel(channel);
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if(logical_channel == nullptr) return false;
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return set_ssel(logical_channel);
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}
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void disable_cs(uint8_t channel) {
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LogicalChannel* logical_channel = get_logical_channel(channel);
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if(logical_channel == nullptr) return;
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if(logical_channel->hw_channel.in_use && !logical_channel->ssel_override) return; //automatic SSel wasn't overridden
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clear_ssel(logical_channel);
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}
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void set_frequency(uint8_t channel, uint32_t frequency) {
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LogicalChannel* logical_channel = get_logical_channel(channel);
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if(logical_channel == nullptr) return;
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SSP_Cmd(logical_channel->hw_channel.peripheral, DISABLE);
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uint32_t prescale, cr0_div, cmp_clk, ssp_clk;
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if (logical_channel->hw_channel.peripheral == LPC_SSP0){
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ssp_clk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_SSP0);
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} else if (logical_channel->hw_channel.peripheral == LPC_SSP1) {
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ssp_clk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_SSP1);
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} else {
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return;
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}
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//find the closest clock divider / prescaler
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cr0_div = 0;
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cmp_clk = 0xFFFFFFFF;
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prescale = 2;
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while (cmp_clk > frequency) {
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cmp_clk = ssp_clk / ((cr0_div + 1) * prescale);
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if (cmp_clk > frequency) {
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cr0_div++;
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if (cr0_div > 0xFF) {
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cr0_div = 0;
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prescale += 2;
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}
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}
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}
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logical_channel->hw_channel.peripheral->CR0 &= (~SSP_CR0_SCR(0xFF)) & SSP_CR0_BITMASK;
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logical_channel->hw_channel.peripheral->CR0 |= (SSP_CR0_SCR(cr0_div)) & SSP_CR0_BITMASK;
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logical_channel->CR0 = logical_channel->hw_channel.peripheral->CR0; // preserve for restore
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logical_channel->hw_channel.peripheral->CPSR = prescale & SSP_CPSR_BITMASK;
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logical_channel->CPSR = logical_channel->hw_channel.peripheral->CPSR; // preserve for restore
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logical_channel->config.ClockRate = ssp_clk / ((cr0_div + 1) * prescale);
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SSP_Cmd(logical_channel->hw_channel.peripheral, ENABLE);
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}
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void read(uint8_t channel, uint8_t *buffer, uint32_t length) {
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transfer(channel, nullptr, buffer, length);
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}
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uint8_t read(uint8_t channel) {
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uint8_t buffer;
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transfer(channel, nullptr, &buffer, 1);
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return buffer;
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}
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void write(uint8_t channel, const uint8_t *buffer, uint32_t length) {
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transfer(channel, buffer, nullptr, length);
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}
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void write(uint8_t channel, uint8_t value) {
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transfer(channel, &value, nullptr, 1);
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}
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void transfer(uint8_t channel, const uint8_t *buffer_write, uint8_t *buffer_read, uint32_t length) {
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LogicalChannel* logical_channel = get_logical_channel(channel);
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if(logical_channel == nullptr) return;
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if((logical_channel->hw_channel.in_use && !logical_channel->ssel_override) || !logical_channel->hw_channel.initialised) return;
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if(!logical_channel->ssel_override) {
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if(!set_ssel(logical_channel)) return;
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}
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if(logical_channel != logical_channel->hw_channel.active_channel) {
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restore_frequency(logical_channel);
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logical_channel->hw_channel.active_channel = logical_channel;
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}
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logical_channel->hw_channel.xfer_config.tx_data = (void *)buffer_write;
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logical_channel->hw_channel.xfer_config.rx_data = (void *)buffer_read;
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logical_channel->hw_channel.xfer_config.length = length;
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(void)SSP_ReadWrite(logical_channel->hw_channel.peripheral, &logical_channel->hw_channel.xfer_config, SSP_TRANSFER_POLLING); //SSP_TRANSFER_INTERRUPT
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if(!logical_channel->ssel_override) {
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clear_ssel(logical_channel->hw_channel.active_channel);
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}
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}
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uint8_t transfer(uint8_t channel, uint8_t value) {
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uint8_t buffer;
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transfer(channel, &value, &buffer, 1);
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return buffer;
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}
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/*
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* Interrupt Handlers
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*/
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extern "C" void ssp_irq_handler(uint8_t hw_channel) {
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SSP_DATA_SETUP_Type *xf_setup;
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uint32_t tmp;
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uint8_t dataword;
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// Disable all SSP interrupts
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SSP_IntConfig(hardware_channels[hw_channel].peripheral, SSP_INTCFG_ROR | SSP_INTCFG_RT | SSP_INTCFG_RX | SSP_INTCFG_TX, DISABLE);
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dataword = (SSP_GetDataSize(hardware_channels[hw_channel].peripheral) > 8) ? 1 : 0;
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xf_setup = &hardware_channels[hw_channel].xfer_config;
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// save status
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tmp = SSP_GetRawIntStatusReg(hardware_channels[hw_channel].peripheral);
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xf_setup->status = tmp;
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// Check overrun error
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if (tmp & SSP_RIS_ROR) {
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// Clear interrupt
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SSP_ClearIntPending(hardware_channels[hw_channel].peripheral, SSP_INTCLR_ROR);
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// update status
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xf_setup->status |= SSP_STAT_ERROR;
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// Set Complete Flag
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hardware_channels[hw_channel].xfer_complete = SET;
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if(!hardware_channels[hw_channel].active_channel->ssel_override) clear_ssel(hardware_channels[hw_channel].active_channel);
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return;
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}
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if ((xf_setup->tx_cnt != xf_setup->length) || (xf_setup->rx_cnt != xf_setup->length)) {
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/* check if RX FIFO contains data */
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while ((SSP_GetStatus(hardware_channels[hw_channel].peripheral, SSP_STAT_RXFIFO_NOTEMPTY)) && (xf_setup->rx_cnt != xf_setup->length)) {
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// Read data from SSP data
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tmp = SSP_ReceiveData(hardware_channels[hw_channel].peripheral);
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// Store data to destination
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if (xf_setup->rx_data != nullptr) {
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if (dataword == 0) {
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*(uint8_t *) ((uint32_t) xf_setup->rx_data + xf_setup->rx_cnt) = (uint8_t) tmp;
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} else {
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*(uint16_t *) ((uint32_t) xf_setup->rx_data + xf_setup->rx_cnt) = (uint16_t) tmp;
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}
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}
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// Increase counter
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if (dataword == 0) {
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xf_setup->rx_cnt++;
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} else {
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xf_setup->rx_cnt += 2;
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}
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}
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while ((SSP_GetStatus(hardware_channels[hw_channel].peripheral, SSP_STAT_TXFIFO_NOTFULL)) && (xf_setup->tx_cnt != xf_setup->length)) {
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// Write data to buffer
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if (xf_setup->tx_data == nullptr) {
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if (dataword == 0) {
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SSP_SendData(hardware_channels[hw_channel].peripheral, 0xFF);
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xf_setup->tx_cnt++;
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} else {
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SSP_SendData(hardware_channels[hw_channel].peripheral, 0xFFFF);
|
||||
xf_setup->tx_cnt += 2;
|
||||
}
|
||||
} else {
|
||||
if (dataword == 0) {
|
||||
SSP_SendData(hardware_channels[hw_channel].peripheral, (*(uint8_t *) ((uint32_t) xf_setup->tx_data + xf_setup->tx_cnt)));
|
||||
xf_setup->tx_cnt++;
|
||||
} else {
|
||||
SSP_SendData(hardware_channels[hw_channel].peripheral, (*(uint16_t *) ((uint32_t) xf_setup->tx_data + xf_setup->tx_cnt)));
|
||||
xf_setup->tx_cnt += 2;
|
||||
}
|
||||
}
|
||||
|
||||
// Check overrun error
|
||||
if (SSP_GetRawIntStatus(hardware_channels[hw_channel].peripheral, SSP_INTSTAT_RAW_ROR)) {
|
||||
// update status
|
||||
xf_setup->status |= SSP_STAT_ERROR;
|
||||
// Set Complete Flag
|
||||
hardware_channels[hw_channel].xfer_complete = SET;
|
||||
if(!hardware_channels[hw_channel].active_channel->ssel_override) clear_ssel(hardware_channels[hw_channel].active_channel);
|
||||
return;
|
||||
}
|
||||
|
||||
// Check for any data available in RX FIFO
|
||||
while ((SSP_GetStatus(hardware_channels[hw_channel].peripheral, SSP_STAT_RXFIFO_NOTEMPTY)) && (xf_setup->rx_cnt != xf_setup->length)) {
|
||||
// Read data from SSP data
|
||||
tmp = SSP_ReceiveData(hardware_channels[hw_channel].peripheral);
|
||||
|
||||
// Store data to destination
|
||||
if (xf_setup->rx_data != nullptr) {
|
||||
if (dataword == 0) {
|
||||
*(uint8_t *) ((uint32_t) xf_setup->rx_data + xf_setup->rx_cnt) = (uint8_t) tmp;
|
||||
} else {
|
||||
*(uint16_t *) ((uint32_t) xf_setup->rx_data + xf_setup->rx_cnt) = (uint16_t) tmp;
|
||||
}
|
||||
}
|
||||
// Increase counter
|
||||
if (dataword == 0) {
|
||||
xf_setup->rx_cnt++;
|
||||
} else {
|
||||
xf_setup->rx_cnt += 2;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// If there more data to sent or receive
|
||||
if ((xf_setup->rx_cnt != xf_setup->length) || (xf_setup->tx_cnt != xf_setup->length)) {
|
||||
// Enable all interrupt
|
||||
SSP_IntConfig(hardware_channels[hw_channel].peripheral, SSP_INTCFG_ROR | SSP_INTCFG_RT | SSP_INTCFG_RX | SSP_INTCFG_TX, ENABLE);
|
||||
} else {
|
||||
// Save status
|
||||
xf_setup->status = SSP_STAT_DONE;
|
||||
// Set Complete Flag
|
||||
hardware_channels[hw_channel].xfer_complete = SET;
|
||||
if(!hardware_channels[hw_channel].active_channel->ssel_override) clear_ssel(hardware_channels[hw_channel].active_channel);
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
extern "C" void SSP0_IRQHandler(void) {
|
||||
HAL::SPI::ssp_irq_handler(0);
|
||||
}
|
||||
|
||||
extern "C" void SSP1_IRQHandler(void) {
|
||||
HAL::SPI::ssp_irq_handler(1);
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -21,7 +21,12 @@
|
|||
#ifndef SPI_PINS_LPC1768_H
|
||||
#define SPI_PINS_LPC1768_H
|
||||
|
||||
#define SOFTWARE_SPI
|
||||
//new config options
|
||||
#define SD_SPI_CHANNEL (HAL::SPI::CHANNEL_2)
|
||||
#define LCD_SPI_FREQUENCY 4000000
|
||||
#define LCD_SPI_CHANNEL (HAL::SPI::CHANNEL_1)
|
||||
|
||||
//#define SOFTWARE_SPI
|
||||
/** onboard SD card */
|
||||
//#define SCK_PIN P0_7
|
||||
//#define MISO_PIN P0_8
|
||||
|
|
|
|||
46
Marlin/src/HAL/spi_api.h
Normal file
46
Marlin/src/HAL/spi_api.h
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
#ifndef _SPI_API_H_
|
||||
#define _SPI_API_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include "HAL_spi_pins.h"
|
||||
|
||||
namespace HAL {
|
||||
namespace SPI {
|
||||
|
||||
enum SPI_CHANNELS {
|
||||
CHANNEL_0 = 0,
|
||||
CHANNEL_1,
|
||||
CHANNEL_2,
|
||||
CHANNEL_3,
|
||||
CHANNEL_4,
|
||||
CHANNEL_5
|
||||
};
|
||||
|
||||
/*
|
||||
* Initialise the hardware layer (pins and peripheral)
|
||||
*/
|
||||
bool initialise(uint8_t channel);
|
||||
|
||||
/*
|
||||
* Allow override of automatic Chip Select
|
||||
*/
|
||||
bool enable_cs(uint8_t channel);
|
||||
void disable_cs(uint8_t channel);
|
||||
|
||||
|
||||
void set_frequency(uint8_t channel, uint32_t frequency);
|
||||
|
||||
void read(uint8_t channel, uint8_t *buffer, uint32_t length);
|
||||
uint8_t read(uint8_t channel);
|
||||
|
||||
void write(uint8_t channel, const uint8_t *buffer, uint32_t length);
|
||||
void write(uint8_t channel, uint8_t value);
|
||||
|
||||
void transfer(uint8_t channel, const uint8_t *buffer_write, uint8_t *buffer_read, uint32_t length);
|
||||
uint8_t transfer(uint8_t channel, uint8_t value);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#endif /* _SPI_API_H_ */
|
||||
Reference in a new issue