SunRed/Marlin-Artillery-M600
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141 commits

Author SHA1 Message Date
Dave Johnson
0456caf0ad Consolidate shared HALs and isolate HAL compile (#11552) 2018-08-20 21:11:12 -05:00
Chris Pepper
5573ef62c6 [2.0.x] PersistentStore update followup (#11549) 2018-08-14 17:54:12 -05:00
Scott Lahteine
834ea7fcea Remove 'const' from PersistentStore::capacity 2018-08-14 04:46:10 -05:00
Dave Johnson
c64199941e Compile only selected PIO environment (#11519) 2018-08-14 03:28:52 -05:00
Scott Lahteine
865ee5985f Followup persistent store with heading, const 2018-08-13 23:55:33 -05:00
Chris Pepper
66d2b48b59 Update PersistentStore api (#11538) 
- Clean up the API to use a `static` class instance to adhere to Marlin convention
- Add `const` position data access for read/write
- Add Storage capacity to the interface
 2018-08-13 17:30:25 -05:00
Andy Shaw
624986d423 Ensure ADC conversion is complete before reading (#11336) 
The current Marlin implementation relies on a timer interrupt to start the ADC conversion and read it. However in some circumstances the interrupt can be delayed resulting in insufficient time being available for the ADC conversion. This results in a bad reading and false temperature fluctuations. These changes make sure that the conversion is complete (by checking the ADC hardware via the HAL) before reading a value.

See: https://github.com/MarlinFirmware/Marlin/issues/11323
 2018-07-26 03:59:19 -05:00
teemuatlut
fbcdf5eaeb Simplify stepper driver per-axis selection 2018-07-25 02:47:43 -05:00
Scott Lahteine
d05e832f29 Add STM32F1 support for SD-based EEPROM 2018-07-06 23:45:47 -05:00
etagle
e7e896e7d7 More tweaks to fastio_Due.h 2018-07-04 17:57:47 -05:00
Scott Lahteine
8a8eae8d97
Implement more fastio_Due macros (#11165) 2018-07-01 01:24:06 -05:00
Scott Lahteine
fc10101b06 Tweaks to fastio_Due.h 2018-06-30 00:15:50 -05:00
Scott Lahteine
99591dc20c
Filter endstops state at all times (#11066) 2018-06-21 20:14:16 -05:00
etagle
a215725df6 Fix stepper pulse timing 
Always honor minimum period on stepper pulse generation, and fix timing calculations

Signed-off-by: etagle <ejtagle@hotmail.com>
 2018-06-12 21:34:24 -05:00
Scott Lahteine
4dbec774b5 HAL_*_TIMER_RATE => *_TIMER_RATE 2018-06-12 16:39:12 -05:00
etagle
99af086cea Add hidden Serial overflow debug options 2018-06-10 04:25:42 -05:00
etagle
d90e8fcad9 Fix XON/XOFF implementation 
Pointed out by @GMagician
 2018-06-10 04:25:42 -05:00
Eduardo José Tagle
d3c02410a8 [2.0.x] Small assorted collection of fixes and improvements (#10911) 
* Misc fixes and improvements

- Get rid of most critical sections on the Serial port drivers for AVR and DUE. Proper usage of FIFOs should allow interrupts to stay enabled without harm to queuing and dequeuing.
  Also, with 8-bit indices (for AVR) and up to 32-bit indices (for ARM), there is no need to protect reads and writes to those indices.
- Simplify the XON/XOFF logic quite a bit. Much cleaner now (both for AVR and ARM)
- Prevent a race condition (edge case) that could happen when estimating the proper value for the stepper timer (by reading it) and writing the calculated value for the time to the next ISR by disabling interrupts in those critical and small sections of the code - The problem could lead to lost steps.
- Fix dual endstops not properly homing bug (maybe).

* Set position immediately when possible
 2018-06-01 19:02:22 -05:00
Scott Lahteine
5f8591528e Remove #pragmas that don't help c files 2018-05-23 23:47:16 -05:00
Scott Lahteine
c89649b46e Suppress U8glib build warnings 2018-05-23 02:47:36 -05:00
etagle
569df3fc0c Fix interrupt-based endstop detection 
- Also implemented real endstop reading on interrupt.
 2018-05-20 07:10:24 -05:00
etagle
0566badcef Add memory barrier, optimal interrupt on-off 
Disabling an ISR on ARM has 3 instructions of latency. A Memory barrier is REQUIRED to ensure proper and predictable disabling. Memory barriers are expensive, so avoid disabling if already disabled (See https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/)
 2018-05-20 02:39:34 -05:00
Scott Lahteine
206014a957 Fix LPC176x timer functions 
Co-Authored-By: ejtagle <ejtagle@hotmail.com>
 2018-05-20 01:58:51 -05:00
Scott Lahteine
59f7861bcb
Move backtrace to the HAL folder (#10790) 2018-05-20 01:33:21 -05:00
Scott Lahteine
50270b53a0 Clear up some more compile warnings 2018-05-17 18:40:49 -05:00
Scott Lahteine
fb608938f8 Prevent compilation of unused u8g-oriented code 2018-05-14 13:31:04 -05:00
Scott Lahteine
37b15fe4cf Reorder HAL timer header items 2018-05-13 16:50:39 -05:00
Scott Lahteine
99ecdf59af Smarter MIN, MAX, ABS macros 
Use macros that explicitly avoid double-evaluation and can be used for any datatype, replacing `min`, `max`, `abs`, `fabs`, `labs`, and `FABS`.

Co-Authored-By: ejtagle <ejtagle@hotmail.com>
 2018-05-13 04:52:56 -05:00
etagle
9d98a62699 Followup to HAL optimizations and delays 
- Cleanups, fixes for Due HAL code.
- TC_IER is write-only. Use TC_IMR to test ISR state.
 2018-05-13 00:46:23 -05:00
Scott Lahteine
a1062eec5b
Better handling of DELAY_NS and DELAY_US (#10716) 
Co-Authored-By: ejtagle <ejtagle@hotmail.com>
 2018-05-12 08:34:04 -05:00
etagle
1b225a2809 DUE: Emergency parser for the USB CDC 2018-05-12 02:12:11 -05:00
Scott Lahteine
0436e16fb2 Apply shorthand Assembler macros 2018-05-08 10:08:54 -05:00
Scott Lahteine
d1b619be52 Standardize some hexadecimals 2018-05-08 09:19:18 -05:00
Scott Lahteine
2578996631
[2.0.x] Emergency parser for multiple serial ports (#10524) 2018-04-25 20:58:00 -05:00
Chris Pepper
2242b98248 [LPC176x] Emergency Parser Feature (#10516) 2018-04-25 06:44:26 -05:00
Eduardo José Tagle
c1e5ebbc1e [2.0.x] AVR: Atomic bit set and clear of upper pin ports without critical section (#10502) 
* AVR: Atomic bit set and clear

The critical section can be dropped, saving 3 cycles per access. Also simplified pin toggling for all ports.
 2018-04-24 13:45:43 -05:00
Eduardo José Tagle
0c428a66d9 Proper AVR preemptive interrupt handling (#10496) 
Also simplify logic on all ARM-based interrupts. Now, it is REQUIRED to properly configure interrupt priority. USART should have highest priority, followed by Stepper, and then all others.
 2018-04-23 22:05:07 -05:00
Chris Pepper
cc6d41e1d3 Use a macro for HAL header redirection (#10380) 2018-04-12 20:25:08 -05:00
Scott Lahteine
9ff4e9e1e6 Patch _IS_HW_SPI so defined() works 2018-04-07 23:29:00 -05:00
Bob-the-Kuhn
acda4ecb20 Fix DUE Trinamic SW/HW SPI sanity check (#10336) 2018-04-06 22:22:30 -05:00
Bob-the-Kuhn
902c885782 Switch to TMC2130 compatible hardware SPI & misc (#10299) 2018-04-04 20:13:27 -05:00
Scott Lahteine
93305a2d5e Fix some spellings 2018-04-02 03:03:37 -05:00
Scott Lahteine
889fd5f71f Backtrace minor cleanup 2018-03-31 18:59:36 -05:00
Eduardo José Tagle
749f19e502 [2.0.x] Move backtrace to a shared location (#10237) 
- And implement the `backtrace()` function call
 2018-03-28 14:13:20 -04:00
etagle
8934a2c49b Added some missing Thumb instructions to the traceback follower, so now it is able to traceback through switch() statements 2018-03-27 04:30:38 -03:00
etagle
328edea03a Several fixes to the backtracer. Tested ant it works 2018-03-26 03:42:54 -03:00
ejtagle
9a24c0ae3f Tons of fixes to the backtracker code, and also added an extra backtracker that does not require unwind tables to work and it is used if unwind tables are absent 2018-03-25 00:52:04 -03:00
Bob-the-Kuhn
f7857ac8a8
Merge pull request #10185 from ejtagle/bugfix-2.0.x 
[2.0.x] DUE debugging: Solve WDT startup delay, add traceback & crash report uses programming port baud rate
 2018-03-24 13:32:34 -05:00
Bob-the-Kuhn
509227fd80 change to mode 0 2018-03-23 09:37:58 -05:00
etagle
c3b23974bd Added detection of case when no unwind tables are available 2018-03-23 05:22:45 -03:00