288 lines
7.5 KiB
C
288 lines
7.5 KiB
C
/**
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* \file
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*
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* \brief Chip-specific PLL definitions.
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*
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* Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#ifndef CHIP_PLL_H_INCLUDED
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#define CHIP_PLL_H_INCLUDED
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#include "osc.h"
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/// @cond 0
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/**INDENT-OFF**/
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**INDENT-ON**/
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/// @endcond
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/**
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* \weakgroup pll_group
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* @{
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*/
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#define PLL_OUTPUT_MIN_HZ 84000000
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#define PLL_OUTPUT_MAX_HZ 192000000
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#define PLL_INPUT_MIN_HZ 8000000
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#define PLL_INPUT_MAX_HZ 16000000
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#define NR_PLLS 2
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#define PLLA_ID 0
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#define UPLL_ID 1 //!< USB UTMI PLL.
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#define PLL_UPLL_HZ 480000000
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#define PLL_COUNT 0x3fU
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enum pll_source {
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PLL_SRC_MAINCK_4M_RC = OSC_MAINCK_4M_RC, //!< Internal 4MHz RC oscillator.
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PLL_SRC_MAINCK_8M_RC = OSC_MAINCK_8M_RC, //!< Internal 8MHz RC oscillator.
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PLL_SRC_MAINCK_12M_RC = OSC_MAINCK_12M_RC, //!< Internal 12MHz RC oscillator.
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PLL_SRC_MAINCK_XTAL = OSC_MAINCK_XTAL, //!< External crystal oscillator.
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PLL_SRC_MAINCK_BYPASS = OSC_MAINCK_BYPASS, //!< External bypass oscillator.
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PLL_NR_SOURCES, //!< Number of PLL sources.
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};
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struct pll_config {
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uint32_t ctrl;
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};
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#define pll_get_default_rate(pll_id) \
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((osc_get_rate(CONFIG_PLL##pll_id##_SOURCE) \
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* CONFIG_PLL##pll_id##_MUL) \
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/ CONFIG_PLL##pll_id##_DIV)
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/* Force UTMI PLL parameters (Hardware defined) */
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#ifdef CONFIG_PLL1_SOURCE
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# undef CONFIG_PLL1_SOURCE
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#endif
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#ifdef CONFIG_PLL1_MUL
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# undef CONFIG_PLL1_MUL
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#endif
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#ifdef CONFIG_PLL1_DIV
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# undef CONFIG_PLL1_DIV
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#endif
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#define CONFIG_PLL1_SOURCE PLL_SRC_MAINCK_XTAL
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#define CONFIG_PLL1_MUL 0
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#define CONFIG_PLL1_DIV 0
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/**
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* \note The SAM3X PLL hardware interprets mul as mul+1. For readability the hardware mul+1
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* is hidden in this implementation. Use mul as mul effective value.
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*/
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static inline void pll_config_init(struct pll_config *p_cfg,
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enum pll_source e_src, uint32_t ul_div, uint32_t ul_mul)
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{
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uint32_t vco_hz;
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Assert(e_src < PLL_NR_SOURCES);
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if (ul_div == 0 && ul_mul == 0) { /* Must only be true for UTMI PLL */
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p_cfg->ctrl = CKGR_UCKR_UPLLCOUNT(PLL_COUNT);
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} else { /* PLLA */
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/* Calculate internal VCO frequency */
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vco_hz = osc_get_rate(e_src) / ul_div;
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Assert(vco_hz >= PLL_INPUT_MIN_HZ);
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Assert(vco_hz <= PLL_INPUT_MAX_HZ);
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vco_hz *= ul_mul;
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Assert(vco_hz >= PLL_OUTPUT_MIN_HZ);
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Assert(vco_hz <= PLL_OUTPUT_MAX_HZ);
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/* PMC hardware will automatically make it mul+1 */
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p_cfg->ctrl = CKGR_PLLAR_MULA(ul_mul - 1) | CKGR_PLLAR_DIVA(ul_div) | CKGR_PLLAR_PLLACOUNT(PLL_COUNT);
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}
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}
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#define pll_config_defaults(cfg, pll_id) \
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pll_config_init(cfg, \
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CONFIG_PLL##pll_id##_SOURCE, \
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CONFIG_PLL##pll_id##_DIV, \
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CONFIG_PLL##pll_id##_MUL)
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static inline void pll_config_read(struct pll_config *p_cfg, uint32_t ul_pll_id)
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{
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Assert(ul_pll_id < NR_PLLS);
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if (ul_pll_id == PLLA_ID) {
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p_cfg->ctrl = PMC->CKGR_PLLAR;
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} else {
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p_cfg->ctrl = PMC->CKGR_UCKR;
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}
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}
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static inline void pll_config_write(const struct pll_config *p_cfg, uint32_t ul_pll_id)
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{
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Assert(ul_pll_id < NR_PLLS);
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if (ul_pll_id == PLLA_ID) {
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pmc_disable_pllack(); // Always stop PLL first!
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PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | p_cfg->ctrl;
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} else {
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PMC->CKGR_UCKR = p_cfg->ctrl;
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}
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}
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static inline void pll_enable(const struct pll_config *p_cfg, uint32_t ul_pll_id)
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{
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Assert(ul_pll_id < NR_PLLS);
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if (ul_pll_id == PLLA_ID) {
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pmc_disable_pllack(); // Always stop PLL first!
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PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | p_cfg->ctrl;
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} else {
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PMC->CKGR_UCKR = p_cfg->ctrl | CKGR_UCKR_UPLLEN;
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}
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}
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/**
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* \note This will only disable the selected PLL, not the underlying oscillator (mainck).
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*/
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static inline void pll_disable(uint32_t ul_pll_id)
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{
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Assert(ul_pll_id < NR_PLLS);
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if (ul_pll_id == PLLA_ID) {
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pmc_disable_pllack();
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} else {
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PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN;
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}
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}
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static inline uint32_t pll_is_locked(uint32_t ul_pll_id)
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{
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Assert(ul_pll_id < NR_PLLS);
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if (ul_pll_id == PLLA_ID) {
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return pmc_is_locked_pllack();
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} else {
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return pmc_is_locked_upll();
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}
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}
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static inline void pll_enable_source(enum pll_source e_src)
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{
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switch (e_src) {
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case PLL_SRC_MAINCK_4M_RC:
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case PLL_SRC_MAINCK_8M_RC:
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case PLL_SRC_MAINCK_12M_RC:
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case PLL_SRC_MAINCK_XTAL:
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case PLL_SRC_MAINCK_BYPASS:
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osc_enable(e_src);
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osc_wait_ready(e_src);
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break;
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default:
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Assert(false);
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break;
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}
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}
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static inline void pll_enable_config_defaults(unsigned int ul_pll_id)
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{
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struct pll_config pllcfg;
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if (pll_is_locked(ul_pll_id)) {
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return; // Pll already running
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}
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switch (ul_pll_id) {
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#ifdef CONFIG_PLL0_SOURCE
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case 0:
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pll_enable_source(CONFIG_PLL0_SOURCE);
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pll_config_init(&pllcfg,
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CONFIG_PLL0_SOURCE,
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CONFIG_PLL0_DIV,
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CONFIG_PLL0_MUL);
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break;
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#endif
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#ifdef CONFIG_PLL1_SOURCE
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case 1:
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pll_enable_source(CONFIG_PLL1_SOURCE);
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pll_config_init(&pllcfg,
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CONFIG_PLL1_SOURCE,
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CONFIG_PLL1_DIV,
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CONFIG_PLL1_MUL);
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break;
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#endif
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default:
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Assert(false);
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break;
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}
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pll_enable(&pllcfg, ul_pll_id);
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while (!pll_is_locked(ul_pll_id));
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}
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/**
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* \brief Wait for PLL \a pll_id to become locked
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*
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* \todo Use a timeout to avoid waiting forever and hanging the system
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*
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* \param pll_id The ID of the PLL to wait for.
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*
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* \retval STATUS_OK The PLL is now locked.
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* \retval ERR_TIMEOUT Timed out waiting for PLL to become locked.
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*/
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static inline int pll_wait_for_lock(unsigned int pll_id)
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{
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Assert(pll_id < NR_PLLS);
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while (!pll_is_locked(pll_id)) {
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/* Do nothing */
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}
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return 0;
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}
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//! @}
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/// @cond 0
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/**INDENT-OFF**/
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#ifdef __cplusplus
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}
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#endif
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/**INDENT-ON**/
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/// @endcond
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#endif /* CHIP_PLL_H_INCLUDED */
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