Commit graph

308 commits

Author SHA1 Message Date
android444
16da5c62d0 Teensy 3.x fastio pullup (#10890) 2018-05-28 16:25:12 -05:00
Scott Lahteine
9b9b62b218 delay(SERVO_DELAY) => safe_delay(servo_delay[servo_index]) 2018-05-28 03:44:32 -05:00
android444
9c235ef821 [HAL]Add support for ST7920 - Teensy 3.x (#10872) 2018-05-27 03:36:57 -05:00
Bob-the-Kuhn
1c0ad8bbae wrong type of exit method 2018-05-26 08:17:03 -05:00
Eduardo José Tagle
6f330f397e [2.0.x] Buffer overflow and scroll fix, UTF8 cleanup (#10844) 2018-05-25 23:32:37 -05:00
Bob Kuhn
235facd545 install AVRDUDE 5.10, faster disk find for LPC1768 (#10849) 2018-05-25 20:26:48 -05:00
Bob Kuhn
e2db509d58 [2.0.x] Update/Fix LPC1768 extra script upload_extra_script.py (#10843)
* Use a different method to find the volume info in Windows
2018-05-25 04:31:18 -05:00
Scott Lahteine
5f8591528e Remove #pragmas that don't help c files 2018-05-23 23:47:16 -05:00
Scott Lahteine
c89649b46e Suppress U8glib build warnings 2018-05-23 02:47:36 -05:00
Scott Lahteine
4118199ddd Tweaks to core headers 2018-05-21 20:32:18 -05:00
Bob Kuhn
6dfbb39f83 [LPC1768] Add error-handling to upload script, update autobuild.py (#10802) 2018-05-20 21:22:04 -05:00
etagle
569df3fc0c Fix interrupt-based endstop detection
- Also implemented real endstop reading on interrupt.
2018-05-20 07:10:24 -05:00
etagle
0566badcef Add memory barrier, optimal interrupt on-off
Disabling an ISR on ARM has 3 instructions of latency. A Memory barrier is REQUIRED to ensure proper and predictable disabling. Memory barriers are expensive, so avoid disabling if already disabled (See https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/)
2018-05-20 02:39:34 -05:00
Scott Lahteine
c2fb2f54a1 Use assembly for AVR ISR vectors
Co-Authored-By: ejtagle <ejtagle@hotmail.com>
2018-05-20 01:58:51 -05:00
Scott Lahteine
206014a957 Fix LPC176x timer functions
Co-Authored-By: ejtagle <ejtagle@hotmail.com>
2018-05-20 01:58:51 -05:00
Scott Lahteine
59f7861bcb
Move backtrace to the HAL folder (#10790) 2018-05-20 01:33:21 -05:00
Scott Lahteine
c173a31060 Fix some compile warnings 2018-05-19 16:54:48 -05:00
Chris Pepper
9b64fdbc3a [LPC176x] HAL: Add missing program space definition (#10776) 2018-05-19 15:37:54 -05:00
Scott Lahteine
50270b53a0 Clear up some more compile warnings 2018-05-17 18:40:49 -05:00
etagle
40d7e12827 Removing warnings from compilation 2018-05-17 18:04:22 -05:00
Scott Lahteine
fb608938f8 Prevent compilation of unused u8g-oriented code 2018-05-14 13:31:04 -05:00
Scott Lahteine
37b15fe4cf Reorder HAL timer header items 2018-05-13 16:50:39 -05:00
Scott Lahteine
883b0c9880
Convert custom maths to inlines (#10728) 2018-05-13 08:10:08 -05:00
Scott Lahteine
99ecdf59af Smarter MIN, MAX, ABS macros
Use macros that explicitly avoid double-evaluation and can be used for any datatype, replacing `min`, `max`, `abs`, `fabs`, `labs`, and `FABS`.

Co-Authored-By: ejtagle <ejtagle@hotmail.com>
2018-05-13 04:52:56 -05:00
etagle
9d98a62699 Followup to HAL optimizations and delays
- Cleanups, fixes for Due HAL code.
- TC_IER is write-only. Use TC_IMR to test ISR state.
2018-05-13 00:46:23 -05:00
Scott Lahteine
a1062eec5b
Better handling of DELAY_NS and DELAY_US (#10716)
Co-Authored-By: ejtagle <ejtagle@hotmail.com>
2018-05-12 08:34:04 -05:00
etagle
1b225a2809 DUE: Emergency parser for the USB CDC 2018-05-12 02:12:11 -05:00
Scott Lahteine
0436e16fb2 Apply shorthand Assembler macros 2018-05-08 10:08:54 -05:00
Scott Lahteine
d1b619be52 Standardize some hexadecimals 2018-05-08 09:19:18 -05:00
Scott Lahteine
81b632c255 Additional temp-oriented improvements 2018-05-02 08:43:22 -05:00
nightdemonx
e911635fb1 Add thermocouple with AD8495 support 2018-05-02 08:43:16 -05:00
Scott Lahteine
3f68203324 Modify FastIO error message 2018-04-28 20:27:36 -05:00
Scott Lahteine
a474a7e675 Correct AVR_ATmega328_FAMILY macro
…as with #10540

Co-Authored-By: per1234 <per1234@users.noreply.github.com>
2018-04-27 03:13:46 -05:00
Scott Lahteine
456cf971af HAL FastIO cleanup and fixes 2018-04-26 00:40:16 -05:00
J.C. Nelson
5b5e322356 Set Interrupt Priorities and Grouping for STM32F103. (#10517) 2018-04-26 00:21:16 -05:00
Scott Lahteine
2578996631
[2.0.x] Emergency parser for multiple serial ports (#10524) 2018-04-25 20:58:00 -05:00
Chris Pepper
2242b98248 [LPC176x] Emergency Parser Feature (#10516) 2018-04-25 06:44:26 -05:00
Eduardo José Tagle
c1e5ebbc1e [2.0.x] AVR: Atomic bit set and clear of upper pin ports without critical section (#10502)
* AVR: Atomic bit set and clear

The critical section can be dropped, saving 3 cycles per access. Also simplified pin toggling for all ports.
2018-04-24 13:45:43 -05:00
Scott Lahteine
a3ce8a3fcd Add sanity checks for EMERGENCY_PARSER 2018-04-24 09:24:26 -05:00
Eduardo José Tagle
0c428a66d9 Proper AVR preemptive interrupt handling (#10496)
Also simplify logic on all ARM-based interrupts. Now, it is REQUIRED to properly configure interrupt priority. USART should have highest priority, followed by Stepper, and then all others.
2018-04-23 22:05:07 -05:00
Scott Lahteine
f423e54f77 Strip trailing spaces 2018-04-23 18:00:43 -05:00
Scott Lahteine
cb46cb8480
Add HAS_HEATED_BED conditional (#10495) 2018-04-23 17:13:01 -05:00
Scott Lahteine
dea686cf55
Define short pin names in fastio for STM32 (#10461) 2018-04-20 14:54:35 -05:00
Karl Andersson
428c54f2ad [2.0.x] HAL for STM32F4 (#10434) 2018-04-17 17:33:29 -05:00
GMagician
20772492aa Fix compile warnings in AVR fastio.h (#10440) 2018-04-17 17:26:57 -05:00
Chris Pepper
c9aed73987 Fix missed includes from HAL macro patch (#10416) 2018-04-15 18:27:34 -05:00
Scott Lahteine
29dda871cb Patch "upload_disk" to make python happy 2018-04-13 22:27:08 -05:00
Chris Pepper
cc6d41e1d3 Use a macro for HAL header redirection (#10380) 2018-04-12 20:25:08 -05:00
Bob-the-Kuhn
85014cd132 [2.0.x] LPC1768 - automatic selection of upload disk (#10374) 2018-04-11 14:41:16 -05:00
Scott Lahteine
44a697ab04 Set STM32F1 TEMP_TIMER_FREQUENCY to 1K
Responding to https://github.com/MarlinFirmware/Marlin/pull/8833#issuecomment-379426803
2018-04-08 01:08:05 -05:00